TOKYO (dpa-AFX) - Advantest Corporation (ATE) a Japanese technology company on Thursday introduced SiConic, a scalable solution for automated silicon validation. Engineered to tackle the growing complexity of advanced SoCs, SiConic empowers design verification and silicon validation engineers to accelerate sign-off with unmatched reliability, efficiency, and collaboration.
Set to debut next week at DVCon in San Jose, California, SiConic reinforces Advantest's dedication to revolutionizing the R&D workflow for its customers.
As SoC complexity, 3D packaging, and heterogeneous integration push traditional validation to its limits, DV and SV teams face mounting pressure to accelerate time-to-market. Despite the potential of pre-silicon verification reuse, the industry lacks automated solutions for seamless implementation. SiConic, partnering with Cadence, Siemens, and Synopsys, bridges this gap-enhancing efficiency and expediting silicon validation.
SiConic Explorer, the platform's software core, streamlines workflows by seamlessly integrating with EDA verification tools like Cadence Perspec System Verifier, leveraging the Accellera PSS standard. It also supports debuggers such as Lauterbach's TRACE32, enabling faster bring-up of complex multi-IP test cases.
SiConic Link is the hardware backbone of the SiConic solution, enabling high-speed functional validation with HSIO capabilities for protocols like PCIe and USB. It supports high-throughput testing, advanced tracing, and debugging with JTAG, SPI, and general-purpose I/Os, providing extensive control and visibility within the target board environment.
SiConic bridges pre- and post-silicon validation, allowing DV engineers to extend functional coverage and SV engineers to seamlessly load, set parameters, and debug silicon content. This highly portable solution scales effortlessly for global R&D teams working on complex SoCs with diverse IP blocks. By enabling data-driven insights and collaborative decision-making, SiConic ensures confident sign-off, fostering customer trust in early samples and long-term system reliability.
At DVCon, February 24-27, Advantest will showcase SiConic in a tutorial hosted by Cadence on February 24 at 1:30 p.m. On February 25 at 3:00 p.m., Advantest, Qualcomm, and Cadence will present a paper titled 'Accelerating Device Sign-off through a Unified Environment for Design Verification, Silicon Validation, and ATE with PSS.' For more details on SiConic and Advantest's full ATE portfolio, visit booth 107 at DVCon.
Leading Advantest IC customers and EDA partners are already leveraging SiConic, experiencing significant gains in performance and productivity.
Industry leaders emphasize the need for new approaches to tackle the growing complexity of multi-chiplet designs and AI-driven applications. AMD's Alex Starr highlights the importance of bridging pre- and post-silicon testing through SiConic's scalable, integrated verification path.
Cadence's Paul Cunningham underscores the escalating quality demands in AI and automotive ADAS, noting that extending PSS-based verification onto silicon with SiConic enhances coverage and design insights. Advantest's Juergen Serrer stresses the necessity of a systematic, automated test flow to streamline silicon bring-up, positioning SiConic as a transformative solution for unifying pre-silicon test development with real-world silicon validation.
Thursday ATE closed at $63.89 or 1.40% higher on the OTCPK.
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